(China (Mainland))
Product Summary
The EPM7064SLC44-10 is a Programmable Logic Device. The EPM7064SLC44-10 of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064SLC44-10 provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
Parametrics
EPM7064SLC44-10 absolute maximum ratings: (1)Supply voltage: –2.0 to 7.0 V With respect to ground; (2)DC input voltage: –2.0 to 7.0 V; (3)DC output current, per pin: –25 to 25 mA; (4)Storage temperature: –65 to 150 ℃; (5)Ambient temperature: –65 to 135 ℃; (6)Junction temperature: Ceramic packages, under bias: 150 ℃, PQFP and RQFP packages, under bias: 135 ℃.
Features
EPM7064SLC44-10 features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices-ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||||
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 EPM7064SLC44-10 |
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IC MAX 7000 CPLD 64 44-PLCC |
Data Sheet |
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EPM7064SLC44-10F |
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IC MAX 7000 CPLD 64 44-PLCC |
Data Sheet |
Negotiable |
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EPM7064SLC44-10N |
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IC MAX 7000 CPLD 64 44-PLCC |
Data Sheet |
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